The connection between a line-switched network and a packet-switched network such as IP (Internet Protocol), for conducting bidirectional communication, is implemented by a gateway apparatus which is for converting a variety of data, such as control information, image encoding information or speech encoding information which are based on the data format of one of the communication networks, into the data format of the other communication network. In this case, the data, including the information of various sorts, is subjected to conversion only of a communication protocol, or to transcoder processing for enabling connection under different encoding systems, as necessary. In such case, insofar as the speech encoded data is concerned, in particular, such a processing method is required in which it is possible to maintain not only the speech quality but also the communication with short delay.
FIG. 11 shows an example of a typical configuration of a conventional gateway apparatus. Referring to FIG. 11, for the direction from a line-switched network to a packet-switched network, data containing the encoded speech information, along with the control information and the encoded image information is multiplexed with a fixed word length and supplied from a line-switched network terminating circuit 100 that is for terminating the line-switched network. The multiplexed data is supplied with a preset period to a multiplexed data demultiplexing circuit 200. This multiplexed data demultiplexing circuit 200 performs processing in accordance with a preset period managed by a first timer circuit 1000. On receipt of a processing start request signal, output from the first timer circuit 1000, the multiplexed data demultiplexing circuit detects a unique word, which is an identifier used for separating multiplexed data from the line-switched network into control data, image data and speech data. Based on the so detected unique word, the multiplexed data demultiplexing circuit performs demultiplexing of the multiplexed data. The data demultiplexed by the multiplexed data demultiplexing circuit 200, that is, the control data, image data and the speech data, are supplied to a control data processing circuit 300, an image data processing circuit 400 and to a speech data processing circuit 500, respectively. The data processing circuits 300, 400 and 500 perform respective data processing operations and output the resulting data to associated packet-switched network terminating circuits 600, 700 and 800, respectively. The packet-switched network terminating circuits 600, 700 and 800 output data received from the data processing circuits 300, 400 and 500 to the packet-switched network, respectively.
On the other hand, for the direction of communication from the packet-switched network to the line-switched network, the respective packets, containing the control information, image encoding information and the speech encoding information, are received by the associated packet-switched network terminating circuits 600, 700 and 800, respectively. The control data, image encoded data and the speech encoded data are output to the control data processing circuit 300, image data processing circuit 400 and to the speech data processing circuit 500, respectively. The data processing circuits 300, 400 and 500 perform the processing operations which are the reverse of those from the line-switched network to the packet-switched network, and output the resulting data. A data multiplexing circuit 900 performs the processing in accordance with the preset period managed by the first timer circuit 1000. On receipt of a processing start request signal, output from the first timer circuit 1000, the data multiplexing circuit 900 multiplexes the data output from the data processing circuits 300, 400 and 500 to output the resulting demultiplexed data to the line-switched network terminating circuit 100. The line-switched network terminating circuit 100 sends the multiplexed data, obtained from the data multiplexing circuit 900, to the line-switched network.
FIG. 12 shows an example of a typical configuration of the speech data processing circuit 500 and the packet-switched network terminating circuit 800. Referring to FIG. 12, for the direction of communication from the line-switched network to the packet-switched network, the speech data processing circuit 500 converts the protocol of the speech encoded data, output from the multiplexed data demultiplexing circuit 200, into that of packet data, in a packet data forming circuit 501. This packet data forming circuit 501 then outputs the resulting packet speech data to a transmission circuit 801 within a packet-switched network speech data terminating circuit 800. The transmission circuit 801 sends out packet data to the packet-switched network.
Insofar as the direction from the packet-switched network to the line-switched network is concerned, a speech packet is received by a receiving circuit 802 of the packet-switched network speech data terminating circuit 800 so as to be stored in a buffer, not shown, provided in the receiving circuit 802. In the speech data processing circuit 500, a second timer circuit 511 is a circuit for outputting a processing start request to an encoded data extracting circuit 512. The encoded data extracting circuit 512 acquires speech data from the receiving circuit 802, at a time point the encoded data extracting circuit 512 has received the processing start request from the second timer circuit 511, extracts the speech encoded data and outputs the so extracted speech encoded data to the data multiplexing circuit 900.
As a gateway apparatus for connecting different type communication networks each other, there have so far been known apparatus of a variety of configurations. For example, there is known a speech gateway apparatus which has an exchanger interfacing unit and a packet controller and which is connected via an exchanger to a telephone terminal and is connected to the IP network for speech communication (see for example the Patent Document 1 below).
There has also been known an error concealment technique in the encoding/decoding of moving images in which, when an error has occurred in transmitting an image sent by an encoder, the image data, which has become unable to be decoded normally, is replaced with image data of a block that has been decoded correctly by a decoder, in order to render the deterioration in the image quality less apparent. In this Patent Document, error concealment control is executed by taking frame correlation into account for improving the image quality (see for example the Patent Document 2 below).
There are also known a variety of techniques for absorbing delay fluctuation. For example, there is known such technique in which, when the receiving time interval has become shorter than the transmitting time interval, a reference packet for recovery wait control is dynamically changed to shorten the time until sending received packets to recovery processing as propagation delay fluctuations are absorbed (see for example the Patent Document 3 below). There is also known a configuration of a media converting device including a telephone network side interfacing circuit, connected to a telephone network, an IP network side interfacing circuit, connected to the IP network, and a speech packet processing circuit, in which the media converting device is connected to a media converting controlling circuit. In this media converting device, the terminals connected in the same device are connected without media conversion to decrease speech deterioration or transmission delay (see for example the Patent Document 3 below).
There is furthermore known a receiving device for generating encoded data when a packet from the network has been delayed. This receiving device includes data inserting means which, when a speech packet from the network is delayed such that original speech data to be output has failed to be assembled, inserts encoded speech data for prohibiting idle time into a continuous data portion of the original speech data which cannot be assembled until arrival of the delayed speech packet. The receiving device further includes data discarding means which, when the data inserting means has inserted the encoded speech data for prohibiting idle time, discards plural small-sized data portions, situated in a preset non-continuous location of the assembled original speech data and continuing for a time corresponding to a time interval equivalent to the encoded speech data inserted by the data inserting means (see for example the Patent Document 5 below). Specifically, the Patent Document 5 shows a speech packet receiving apparatus intended to eliminate the problem that, if, in case underrun has occurred, delayed packets that failed to be absorbed are discarded, and substitute speech data are written in place of the delayed packet data, the amount of discarded speech data may be increased in case the discarded speech data are compressed encoded data, thus deteriorating the speech quality. To this end, the Patent Document discloses a speech packet receiving apparatus, in which the packets arriving from the network are decoded to PCM (Pulse Code Modulation) data and the resulting PCM data are output at a preset transmission speed for lowering the deterioration in the speech quality. The speech packet receiving apparatus includes an encoded speech buffer for absorbing the difference in the packet incoming time within an extent of not detracting from real-time performance, and a PCM level comparator for comparing whether or not decoded PCM data is of a speech level close to silent data which does not affect the speech quality and which therefore may safely be discarded. The speech packet receiving apparatus also includes a decimating counter controller which, when the substitute encoded PCM data is inserted, discretely decimates an amount of nearly silent PCM data corresponding to the amount of the decoded data of the inserted substitute data, at a preset time interval, based on the results of comparison by the PCM level comparator.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2002-290550A (page 4, FIG. 1)
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2002-77922A (page 3, FIG. 1)
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-P2002-185498A (pages 4-5, FIG. 1)
[Patent Document 4]
Japanese Patent Kokai Publication No. JP-P2001-326724A (pages 4-5, FIG. 1)
[Patent Document 5]
Japanese Patent Kokai Publication No. JP-P2000-124947A (pages 2-3, FIG. 1)